Theses Proposals

This page reports (as much as I can) about vacant theses assignments which can be carried out with the instructor. For additional information, come to office hours or send an email to the instructor.

Message To Prospective Students

My research program is very software-intensive, focusing largely in the area of parallel and distributing computing, performance evaluation, modeling and computer simulation, computer architectures, operating systems. If you wish to work with me on a Master’s Thesis, please consider the following checklist before:

  • I am not scared to write in C, and I have a strong desire to work with software very intensely.
  • I have been exposed to some low-level assembly language programming like x86 or ARM, MIPS or other, and it has been an interesting expecience.
  • I have been using UNICES (Linux, FreeBSD or other variants) happily for a while.
  • I have been exposed to parallel programming ( pthreads, MPI, OpenMP).
  • I have fun with algorithms.
  • I’m not scared by mathematical and logical modeling.

If your recognize yourself (even partially) in the above profile, or if you would like to increase your skills in some of the above points, please send me an email!

I look forward to hearing from you!

Theses Topics at a glance

High Performance Simulation

Theses in the field of High Performance Simulation tackles topics related to the design and development of distributed and highly-parallel runtime environments to support the execution of generic simulation models according to a speculative processing paradigm. Some theses target the definition and implementation of simulation models relying on this paradigm.

To get more information on this thesis topic, you can read the following papers: 1 2 3 4 5 6.

  1. NUMA Aware Load-Sharing Policy
    In this thesis, a decision-making module should be designed and implemented. The goal is to determine, at runtime, the best-suited placement for LPs, worker threads, and memory pages in a NUMA architecture. See this supporting material for an additional framing of the topic: 1.
  2. Model-related fossil collection
    This thesis tackles the design and implementation of a transparent module to allow simulation models to perform fossil collection.
  3. Spiking Neural Networks
    Spiking neural networks (SNN) are among the most computationally intensive types of simulation models, with node counts on the order of up to 10^11. This thesis tackles the implementation of efficient runtime environments for SNN simulation on parallel and distributed architectures. See this supporting material for an additional framing of the topic: 1, 2.
  4. Termination Detection
    In speculative simulation, accurate termination detection could be an issue, performancewise. This thesis tackles the design of different algorithms which allow to identify a global termination condition in a model-independent way, with different accuracy/performance tradeoffs. See this supporting material for an additional framing of the topic: 1, 2.

Energy Efficiency

Theses in this field tackle with the problem of identifying a suitable trade-off between performance and energy consumption. The body of work in this area targets methodologies and techniques to allow for an automatic identification of the power/energy/performance level which maximizes the overall efficiency of the application.

To get more information on this thesis topic, you can read the following papers: 1 2 3 4.

  1. Daemon to manage consumption
    Define an interface for low-overhead power management of the system. Define masks to set P-state of multiple cores with a single system call. The daemon should communicate with non-root process to allow them to self-tune power without required superuser privilege. In addition to P-state, should also allow enabling or disabling SMT and turbo boost.
  2. Fine-grain Simultaneous Multi Threading
    SMT can increase applications performance by up to 40% (Intel HT 2 way) with very limited increase in power consumption. However this speed-up is highly performance-dependent and its use might even lead to a performance degradation. Moreover, applications generally are typically composed of different threads which might show a different workload, and thus, different SMT effectiveness. The goal of this thesis is to allow portions of threads of a single application to enable SMT while for others it is still disabled. This could either be achieved at system level (TCB and scheduler modifications) or with an external module and affinity. Measuring the performance/power trade-offs for different applications is also part of this thesis.
  3. Effective exploration of P-state configurations
    In the context of multi-threaded applications, we want to build an exploration policy which does not violate a specified power cap while collecting the data to support the prediction model.
  4. Advanced exploration-based powercap
    Devising exploration strategies which are resilient to local maxima/minima to build prediction model of massively parallel p-state configurations.
  5. Synthetic Benchmark Generation from real-world applications
    The goal of this thesis is to generate a synthetic program starting from a real application, which has a very short duration but is meaningful from a workload point of view with respect to the original application. This generation shall be done using hardware performance counters. See this supporting material for an additional framing of the topic: 1 2.

Non-Blocking Algorithms

Non-blocking algorithms are a family of concurrent algorithms which enforce correctness by relying on fine-grain synchronization hardware instructions, globally termed Read-Modify-Write instructions. Theses in this family address the implementation of data structures which support a massive number of concurrent operations by relying on this form of fine-grain synchronization.

To get more information on this thesis topic, you can read the following papers: 1 2

  1. Locality-aware non-blocking priority queue
    The goal of this thesis is to design and implement a non-blocking priority queue which exhibits increased performance thanks to the exploitation of memory locality.

Heterogeneous Architectures

Heterogeneous architectures are computer architecture in which there are several different families of processing units (CPUs, GPUs, Coprocessors, low-energy cores, etc.) which can be exploited simultaneously. The theses reported here target this family of architectures.

  1. Time Warp on GPU
    Implementation of a GPU-oriented Time Warp scheduler (see the support material in the section on High Performance Simulation for a description of Time Warp).
  2. Hybrid Binary
    Definition and implementation of software support to generate and manage hybrid binaries for heterogeneous architectures.

Computer Architectures

No theses available at the moment.

Cybersecurity

  1. Unveil()
    Design and implementation of a BSD unveil()-like system to support mandatory filesystem access.
  2. Security against Malicious Loadable Kernel Modules
    Design and implementation of a set of patches to protect the Linux kernel from malicious modules.

Theses Archive

Below, you can find a list of Bachelor’s (a selection), Master’s, and PhD thesis which I have been involved in supervising, or which belong to my research group. They could serve as an indication of the kind of work which is carried out by my research group.

2020

[PhD Thesis] R. Marotta, “Innovative Algorithms for Shared Data Structures in Multi-core Platforms,” phdthesis, Sapienza, University of Rome, 2020. [Bibtex]
Supervisor: F. Quaglia - Co-Supervisor: A. Pellegrini
[PhD Thesis] S. Economo, “Techniques and tools for program tracing and analysis with applications to parallel programming,” phdthesis, Sapienza, University of Rome, 2020. [Bibtex]
Supervisor: F. Quaglia - Co-Supervisor: A. Pellegrini
[MSc Thesis] L. Altamura, “Asymmetric Runtime Environments for Increased-Performance Speculative PDES,” mathesis, Sapienza, University of Rome, 2020. [PDF] [Bibtex] [Abstract]
Supervisor: A. Pellegrini. Co-Supervisor: S. Conoci
[MSc Thesis] U. Mazziotta, “Parallel Priorities: Optimizing Priority Queues for NUMA Machines,” mathesis, Sapienza, University of Rome, 2020. [PDF] [Bibtex] [Abstract]
Supervisor: A. Pellegrini - Co-Supervisor: R. Marotta

2019

[PhD Thesis] D. Cingolani, “A new approach to reversible computing with applications to speculative parallel simulation,” phdthesis, Sapienza, University of Rome, 2019. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisor: A. Pellegrini
[PhD Thesis] M. Ianni, “Share-everything Parallel Discrete Event Simulation on Multi-core Machines,” phdthesis, Sapienza, University of Rome, 2019. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisor: A. Pellegrini
[MSc Thesis] S. Ferracci, “Detecting Cache-based Side Channel Attacks using Hardware Performance Counters,” mathesis, Sapienza, University of Rome, 2019. [PDF] [Bibtex] [Abstract]
Supervisor: A. Pellegrini - Co-Supervisor: S. Carnà
[MSc Thesis] A. Piccione, “An Agent-Based Simulation API for Speculative PDES Runtime Environments,” mathesis, Sapienza, University of Rome, 2019. [PDF] [Bibtex]
Supervisor: A. Pellegrini

2018

[MSc Thesis] S. Carnà, “HOP - Hardware-based Online Profiling of multi-threaded applications via AMD Instruction-Based Sampling,” mathesis, Sapienza, University of Rome, 2018. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisor: S. Economo
[MSc Thesis] M. Principe, “Transparent Distributed Cross-State Synchronization in Optimistic Parallel Discrete Event Simulation,” mathesis, Sapienza, University of Rome, 2018. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisor: A. Pellegrini

2017

[MSc Thesis] E. Silvestri, “Fine-Grain Time-Shared Execution of In-Memory Transactions,” mathesis, Sapienza, University of Rome, 2017. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisors: S. Economo, A. Pellegrini, P. Di Sanzo
[MSc Thesis] S. Conoci, “Efficient Software Transactional Memory via Thread Scheduling and Dynamic Voltage and Frequency Scaling,” mathesis, Sapienza, University of Rome, 2017. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisor: P. Di Sanzo
[MSc Thesis] S. Rivieccio, “Energy Efficient Spin-Locking in Multi-Core Machines,” mathesis, Sapienza, University of Rome, 2017. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisor: P. Di Sanzo
[MSc Thesis] A. Scarselli, “A Lock-Free Buddy System for Scalable Memory Allocation,” mathesis, Sapienza, University of Rome, 2017. [PDF] [Bibtex] [Abstract]
Supervisor: B. Ciciani - Co-Supervisor: F. Quaglia, M. Ianni, R. Marota
[MSc Thesis] T. Tocci, “ORCHESTRA: An Asynchronous Wait-Free Distributed GVT Algorithm,” mathesis, Sapienza, University of Rome, 2017. [PDF] [Bibtex] [Abstract]
Supervisor: B. Ciciani - Co-Supervisor: A. Pellegrini

2016

[MSc Thesis] R. Marotta, “A Lock-Free O(1) Priority Queue for Pending Event Set Management,” mathesis, Sapienza, University of Rome, 2016. [PDF] [Bibtex]
Supervisor: F. Quaglia - Co-Supervisors: P. Di Sanzo, A. Pellegrini
[MSc Thesis] N. Marziale, “Dynamic Clustering of Simulation Objects in Speculative Parallel Simulation Systems,” mathesis, Sapienza, University of Rome, 2016. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisor: A. Pellegrini
[MSc Thesis] F. Nobilia, “Runtime Management of Simulation Objects Cross-State Dependencies in NUMA-oriented Parallel Simulation Platforms,” mathesis, Sapienza, University of Rome, 2016. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisor: A. Pellegrini

2015

[MSc Thesis] M. Ianni, “Transactional Memory Based Speculative Parallel Execution of Discrete Event Applications,” mathesis, Sapienza, University of Rome, 2015. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisor: A. Pellegrini
[MSc Thesis] S. Economo, “Lightweight approximate virtual page access tracing of multi-threaded applications via static binary instrumentation,” mathesis, Sapienza, University of Rome, 2015. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisor: A. Pellegrini
[MSc Thesis] A. La Rizza, “Elastic cloud resources provisioning for life insurance undertaking applications,” mathesis, Sapienza, University of Rome, 2015. [PDF] [Bibtex] [Abstract]
Supervisor: B. Ciciani - Co-Supervisors: A. Pellegrini
[MSc Thesis] L. Forte, “Proactive Workload Management in Cloud Environments in the Presence of Software Aging,” mathesis, Sapienza, University of Rome, 2015. [PDF] [Bibtex] [Abstract]
Supervisor: B. Ciciani - Co-Supervisors: P. Di Sanzo, A. Pellegrini
[BSc Thesis] A. Scarselli, “Gestione ottimizzata della delivery e del buffering dei messaggi in piattaforme multi-thread in architetture NUMA,” bathesis, Sapienza, University of Rome, 2015. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisor: A. Pellegrini

2014

[PhD Thesis] A. Pellegrini, “Techniques for Transparent Parallelization of Discrete Event Simulation Models,” phdthesis, Sapienza, University of Rome, 2014. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia
[PhD Thesis] S. Peluso, “Efficient Protocols for Replicated Transactional Systems,” phdthesis, Sapienza, University of Rome, 2014. [PDF] [Bibtex] [Abstract]
Supervisors: F. Quaglia, P. Romano
[PhD Thesis] D. Rughetti, “Autonomic Concurrency Regulation in Software Transactional Memories,” phdthesis, Sapienza, University of Rome, 2014. [PDF] [Bibtex] [Abstract]
Supervisor: B. Ciciani
[MSc Thesis] D. Cingolani, “Application Transparent and Efficient Mixed State-Saving in Speculative Simulation Platforms,” mathesis, Sapienza, University of Rome, 2014. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisor: A. Pellegrini

2013

[PhD Thesis] R. Vitali, “Design of Software Support Structures for High Performance Optimistic Simulations with Special Focus on Multi-Core Hosting Environment,” phdthesis, Sapienza, University of Rome, 2013. [Bibtex] [Abstract]
Supervisor: F. Quaglia

2012

[PhD Thesis] P. Di Sanzo, “Performance Models of Concurrency Control Protocols for Transaction Processing Systems,” phdthesis, Sapienza, University of Rome, 2012. [PDF] [Bibtex] [Abstract]
Supervisor: B. Ciciani
[PhD Thesis] R. Palmieri, “Speculative Protocols for Actively Replicated Transactional Systems,” phdthesis, Sapienza, University of Rome, 2012. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia
[MSc Thesis] P. Stroia, “Securing the IDT and the System Call Table from malicious LKMs,” mathesis, Sapienza, University of Rome, 2012. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisor: A. Pellegrini

2011

[MSc Thesis] A. Porfirio, “Progettazione e implementazione di un meccanismo di rollback parziale per memorie software transazionali,” mathesis, Sapienza, University of Rome, 2011. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisors: P. Di Sanzo, A. Pellegrini
[MSc Thesis] G. Cerasuolo, “Cache-Aware Memory Manager for Optimistic Simulations,” mathesis, Sapienza, University of Rome, 2011. [Bibtex]
Supervisor: F. Quaglia - Co-Supervisors: A. Pellegrini, R. Vitali
[BSc Thesis] F. Visca, “Tecniche di instrumentazione statica per il supporto alla trasparenza verso il programmatore nelle STM,” bathesis, Sapienza, University of Rome, 2011. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia - Co-Supervisors: A. Pellegrini, R. Palmieri

2010

[MSc Thesis] A. Pellegrini, “Salvataggio e Ripristino Autonomico dello Stato degli Oggetti nei Sistemi di Simulazione Ottimistici,” mathesis, Sapienza, University of Rome, 2010. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia
[MSc Thesis] S. Peluso, “missing record,” mathesis, Sapienza, University of Rome, 2010. [Bibtex]
Supervisor: F. Quaglia
[MSc Thesis] D. Didona, “missing record,” mathesis, Sapienza, University of Rome, 2010. [Bibtex]
Supervisor: F. Quaglia

2008

[MSc Thesis] R. Vitali, “missing record,” mathesis, Sapienza, University of Rome, 2008. [Bibtex]
Supervisor: F. Quaglia
[MSc Thesis] D. Rughetti, “Raccolta ed elaborazione di dati provenienti da reti di sensori distribuiti,” mathesis, Sapienza, University of Rome, 2008. [PDF] [Bibtex] [Abstract]
Supervisor: B. Ciciani - Co-Supervisor: P. Romano
[MSc Thesis] R. Palmieri, “Modellazione e valutazione di DBMS relazionali basati su lock e pattern di accesso non uniformi,” mathesis, Sapienza, University of Rome, 2008. [PDF] [Bibtex] [Abstract]
Supervisor: B. Ciciani
[BSc Thesis] A. Pellegrini, “Tracciamento trasparente ed efficiente di scritture su memoria dinamica con granularità arbitraria in architetture per il calcolo ottimistico,” bathesis, Sapienza, University of Rome, 2008. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia

2007

[PhD Thesis] P. Romano, “Protocols for End-To-End Reliability in Multi-Tier Systems,” phdthesis, Sapienza, University of Rome, 2007. [PDF] [Bibtex] [Abstract]
Supervisor: F. Quaglia

2006

[BSc Thesis] R. Palmieri, “MicroOpGen tool and developing extensions for DisSimulator, a simulator for PD32 educational-processor,” bathesis, Sapienza, University of Rome, 2006. [Bibtex]
Supervisor: B. Ciciani

2003

[PhD Thesis] A. Santoro, “Semi-Asynchronous Checkpointing for Optimistic Parallel Simulation,” phdthesis, Sapienza, University of Rome, 2003. [Bibtex]
Supervisor: B. Ciciani

1999

[PhD Thesis] F. Quaglia, “Consistent Checkpointing in Distributed Computations: Theoretical Results and Protocols,” phdthesis, Sapienza, University of Rome, 1999. [PDF] [Bibtex] [Abstract]
Supervisor: B. Ciciani
[PhD Thesis] M. Romero, “Disparity/Motion Estimation for Stereoscopic Video Processing,” phdthesis, Sapienza, University of Rome, 1999. [Bibtex]
Supervisor: B. Ciciani

1998

[PhD Thesis] G. Battaglini, “Analysis of Manufacturing Yields Evaluation of VLSI/WSI Systems: Methods and Methodologies,” phdthesis, Sapienza, University of Rome, 1998. [Bibtex]
Supervisor: B. Ciciani

1995

[MSc Thesis] F. Quaglia, “Passo ottimo del salvataggio dello stato nel tool SIMCOR,” mathesis, Sapienza, University of Rome, 1995. [Bibtex]
Supervisor: B. Ciciani